Chapter 4 : AT89S8253 Microcontroller

Introduction

Today, after more than 20 years of continuous improvement, the 8051 microcontroller is being manufactured across the world by many companies and under different trademarks. Of course, the latest models are by far more advanced than the original one. Many of these models are labeled as “8051 compatible”, “8051 compliant”or “8051 family” in order to emphasize their “noble heritage”. The tags should imply that microcontrollers have similar architecture and are programmed in a similar way, using the same instruction set. In practice, if you know how to handle one of them, you will be able to handle any other belonging to 8051 family, which encompasses several hundreds of different models!

This book covers one model named AT89S8253, manufactured by Atmel. Why this particular one? Because it is widespred, cheap and uses Flash memory for program storage. This last feature makes it ideal for experimentation due to the fact that program can be loaded and erased a number of times. Besides, thanks to the built-in SPI System (Serial Programing Interface), program can be loaded to the microcontroller even if the chip has already been embedded in the final device.

4.1 AT89S8253 Microcontroller ID

• Compatible with 8051 family.
• 12Kb of Flash Memory for program storage.
  • Program is loaded via SPI System (Serial Peripheral Interface).
  • Program may be loaded / erased up to 1000 times.
• 2Kb of EEPROM Memory
• Power Supply Voltage: 4 - 6V.
• Operating clock frequency: 0 - 24MHz.
• 256 bytes of internal RAM for storing variables.
• 32 input/output lines.
• Three 16-bit Timers / Counters.
• 9 interrupt sources.
• 2 additional power saving modes (Low-power Idle and Power-down Mode).
• Programmable UART serial communication.
• Programmable Watchdog Timer.
• Three-level Program Memory Lock

Packages in which AT89S53 appears on the market.

4.2 Pin Description

VCC Power supply voltage (4-6V)
GND Ground ( Negative supply pole)

Port 0 (P0.0-P0.7) If configured as output, each of these pins can be connected up to 8 TTL inputs. If configured as input, the pins can be used as high-impedance inputs as their potential is undefined relative to the ground, i.e. these inputs are floating. If additional (external) memory is used, these pins are used for alternate transfer of data and addresses (A0-A7) for accessing this additional memory chip. Signal on ALE pin determines what and when will be transferred on the port.

Port 1 (P1.0-P1.7) If configured as output, each of these pins can be connected up to 4 TTL inputs. When configured as input, these pins act as standard TTL inputs, that is, each of them is internally connected to the positive supply voltage via relatively high impedance resistor. The voltage on these inputs is 5V. Also, this Port 1 pins have alternate functions as shown in the table below :

Port Pin	Alternate Function
P1.0	T2 (Timer 2 input)
P1.1	T2EX (Timer 2 control input)
P1.4	SS (SPI system control input)
P1.5	MOSI (SPI system I/O)
P1.6	MISO (SPI system I/O)
P1.7	SCK (SPI system clock signal)

Port 2 (P2.0-P2.7) If configured as input or output, this port is identical to Port 1. If external memory is used, Port 2 stores the higer address byte (A8-A15) for addressing additional memory chip.

Port 3 (P3.0-P3.7) Similar to P1, Port 3 pins can be used as universal input or output, but also have additional functions which will be explained later in the chapter.

Port Pin	Alternate Function
P3.0	RXD (serial input)
P3.1	TXD (serial output)
P3.2	INT0 (external interrupt 0)
P3.3	INT1 (external interrupt 1)
P3.4	T0 (Timer 0 external input)
P3.5	T1 (Timer 1 external input)
P3.6	WR (External data memory write signal)
P3.7	RD (External data memory read signal)

RST Logic one (1) on this pin resets the microcontroller.

ALE/PROG In normal operation, this pin emits a pulse sequence with a frequency equal to 1/6 of the main oscillator frequency. If additional memory is used, signal from this pin controls the additional register for temporary storage of the lower address byte (A0-A7). During writing program to the microcontroller, this pin also serves as a control input.

PSEN This pin signal is used for reading from external program memory (ROM).

EA/VPP When this pin is connected to the ground, the microcontroller takes program instructions from external program memory. In case that internal program memory is used (common case), this pin should be connected to the positive supply voltage (VCC). During loading program to internal Flash mamory, this pin is supplied with +12V.

XTAL 1 This is internal oscillator input. It is used for synchronizing the microcontroller with another circuit or when the external oscillator which generates clock pulses is for some reason used.

XTAL 2 This pin is connected to internal oscillator output. In case that external oscillator is used, this pin is out of use.

4.3 AT89S8253 Microcontroller Memory Organisation

ROM (Program Memory)

Program memory with a capacity of 12Kb is designed in FLASH technology, which enables a great number of writing to/erasing up programs. It is programmed via embedded SPI module (Serial Peripheral Interface). Although, it is possible to add external ROM memory chip, 12Kb is more than enough.

RAM (Random Access Memory)

This memory consists of 3 blocks with 128 registers each, and structure that falls into the 8051 Standard:

• 128 general-purpose registers
• 128 memory locations reserved for SFRs. Even though only some of them are trully used, the free ones shouldn’t be used for storing variables.
• 128 additional registers free to be used (have no special purpose). They have the same addresses as SFRs, but are accessed by indirect

EEPROM Memory

EEPROM is a special type of memory, having features of both RAM and ROM. The data are being written to and erased during operation, but saved after the power is turned off. This microcontroller has total of 2K of EEPROM (2048 locations).

Memory Extension

Taking into account that AT89S8253 microcontroller is based on the 8051 core, all mentioned before for this model’s ROM and RAM memory extension remains in force. Meaning that both memories can be added as external chips with the capacity up to 64Kb. Addressing is also the same as in the 8051 Standard.

Types of addressing

Similar to all the microcontrollers compatible with the 8051, there are two ways of addressing:

• Direct (for example: MOV A,30h)
• Indirect (for example: MOV A,@R0)

4.4 SFRs (Special Function Registers)

The AT89S8253 microcontroller has total of 40 Special Function Registers. For the sake of the compatibility with eather 8051 models, the basic group of registers (22 of them ) kept their functions and addresses, while the rest were added to manage new functions of the microcontroller.

As shown in the table above, each of these registers has its name and specific address in RAM. Unoccupied locations are intended for future expansions and new models of the microcontroller and shouldn’t be used. This chapter covers “general” SFRs’ function.

Specialized registers as the ones controlling timers or SPI will be described in the following chapters.

ACC (Accumulator)

Accumulator is designated as ACC or A and belongs to the basic register group of the 8051 core. There are no changes on bits of this register.

B register

B register also belongs to the basic register group of the 8051 core and there are no changes on its bits. Instructions of multiplication and division (MUL and DIV instructions) can be applied only to operands located in registers A and B.

PSW register (Program Status Word)

PSW register belongs to the basic register group of the 8051 core. There are no changes on bits of this register.

SP registar (Stack Pointer)

SP Register belongs to the basic register group of the 8051 core. There are no changes on bits of this register.

Registers P0, P1, P2, P3

Every bit of these registers corresponds to one of the ports pins having the same name. These registers are therefore used for comminicating to peripheral environment by copying data from registers to corresponding pins and vice versa. The registers belongs to the basic register group of the 8051 core and there are no changes on their bits.

R registers (R0 - R7)

They belong to the basic register group of the 8051 core. There are no changes on their bits.

AUXR register (Auxiliary register)

The AUXR register contains only two active bits:

• DISALE
  • 0 - Pulse sequence with the frequency equal to 1/6 of the quartz oscillator frequency appears on ALE.
  • 1 - Pin ALE is active only during execution of MOVX or MOVC instructions.
• Intel_Pwd_Exit
  • 0 - When the microcontroller is in Power Down mode, the program proceeds with execution after the falling edge signal appears (1-0).
  • 1 - When the microcontroller is in Power Down mode, the program proceeds with execution after the raising edge signal appears (0-1).

CLKREG register (Clock Register) X2

• 0 - The oscillator frequency (at XTAL1 pin) is divided by 2 before it is used as clock (machine cycle lasts for 6 such periods).
• 1 - The oscillator signal is directly used as clock generator. In this way, for the same microcontroller’s operating rate, a quartz crystal for two times lower frequency may be used (for example 6MHz instead of 12MHz).

Data Pointers

Data Pointers are not true registers because they don’t physically exist. They consist of two separate registers: DPH (Data Pointer High) and DPL (Data Pointer Low). Data Pointer’s 16 bits are used for addressing external memory and internal EEPROM memory. DPS bit located in the EECON register is in command which registers are to be used as data pointers:

DPS=0 -> Data pointer consists of DP0L and DP0H registers and is designated as DPTR0.

DPS=1 -> Data pointer consists of registers DP1L and DP1H and is designated as DPTR1.

Handling EEPROM memory

2 Kb of on-chip EEPROM memory enable this microcontroller to be used in devices which have to permanently store runtime data. All data stored in this memory will be saved even after the power supply is off and the producer warrants at least 100 000 writing cycles. It is easy for use since there are only a few control bits enabling it.

EEPROM write and read is controlled by EECON special function register. Since the process of programming of EEPROM is relatively slow (writing to one register takes approximately 4mS), a small hardware trick is done in order to enhance it. When bit EELD in EECON is set, the data is not directly written to EEPROM registers but loaded in a small buffer (temporary memory) with the capacity of 32 bytes. When this bit is cleared, the first data following it will be normally written ( takes 4 mS). Also, all registers currently loaded in the buffer will be written simultaneously. In this way, all 32 bytes require only 4mS to be written instead of 128mS required in single byte writing.

EEPROM memory is treated as external memory and that’s why a special instruction for handling additional memory chip (MOVX) is used. The EEMEN bit in the EECON register controlls whether the data will be written/read from an true additional chip or on-chip EEPROM memory.

EECON register

This register’s bits controls the operation of EEPROM memory:

WRTINH

This bit can be read only. When the power supply level is too low for programming of EEPROM, hardware automatically clears the bit, which means that programming can not be executed or that ongoing programming will be aborted.

RDY/BSY

This bit can be read only.

• 0 - Programming is in progress (takes approximately 4mS).
• 1 - Programming is completed (data is written to EEPROM).

DPS

• 0 - Address for programming or reading from EEPROM is stored in the DP0H and DP0L registers.
• 1 - Address for programming or reading from EEPROM is stored in the DP1H and DP1L registers.

EEMEN

• 0 - Instruction MOVX is used for accessing external memory chip.
• 1 - Instruction MOVX is used for accessing internal EEPROM memory. If register addess is greater than 2K, the microcontroller will access external memory.

EEMWE

When set, EEMWE bit enables writing data to EEPROM. The MOVX instruction is used for data writing. After EEPROM write is completed, the bit needs to be cleared from within the program.

EELD

When set, EELD bit enables writing up to 32 bytes simultaneously. When bit is set, the MOVX instruction will not initiate programming of EEPROM, it will just load data to the data buffer of EEPROM memory. Before writing the last data, the bit is cleared and upon the last MOVX, the entire buffer is automatically programmed to EEPROM for 4mS.

4.5 Watchdog Timer (WDT)

Watch-dog timer uses pulses from the quartz oscillator. After Reset and during Power Down Mode, this timer is disabled and has no effect on the program execution. When enabled, a well known battle against the time starts and timer is always “loose”. If program works properly. In this case, the program will always manage reset watchdog timer on time. Otherwise, if watch-dog timer manages to count a full cycle, it indicates that the program doesn’t work properly for some reason. Then WDT comes into force and resets the microcontroller. Obviously, the point is to set instruction in the main program loop which will unceasingly reset the watch-dog timer. In practice, several bits of WDTCON register control this simple and efficient mechanism.

Three bits (PS2, PS1 and PS0) which are in control of prescaler, determine the most important feature of Watch-dog timer- so called nominal time, i.e. time needed to count a full cycle.

The values in the table are valid in case that quartz crystal with frequency of 12MHz is used.

Prescaler Bits			Nominal Time
PS2	PS1	PS0
0	0	0	16ms
0	0	1	32ms
0	1	0	64ms
0	1	1	128ms
1	0	0	256ms
1	0	1	512ms
1	1	0	1024ms
1	1	1	2048ms

WDTCON (Watchdog Control Register) PS2,PS1,PS0

These bits are in control of prescaler and define so called nominal time of the Watchdog timer. If the program doesn’t clear WSWRST bit during that time, this timer will reset the microcontroller. (When all three bits are cleared to 0, the watch-dog timer has a nominal period of 16K machine cycles. When all three bits are set to 1, the nominal period is 2048K machine cycles).

WDIDLE

This bit enables/disables the Watch-dog Timer in Idle mode:

• 0 - Watch-dog timer continues to count in Idle mode (power consumption control).
• 1 - InstructionWatch-dog timer is halted while the microcontroller is in Idle mode.

DISRTO

This bit enables/disables reset of external electronic circuits (out of the microcontroller) connected to the RST pin:

• 0 - Watch-dog controls state of the reset pin. This means that, at the moment of reset, this pin is driven high and acts for a short time as output. In that way, the micro controller as well as all other circuits connected to the RST pin are reset.
• 1 - Reset which generates Watch-dog doesn’t affect state of the reset pin. Watch-dog resets only the microcontroller while the reset pin continues acting as input.

HWDT

This bit selects hardware or software mode for the Watch-dog Timer:

• 0 - Watch-dog is in so called software mode, meaning that it can be enabled or disabled by simply setting or clearing WDTEN bit.
• 1 - Watch-dog is in so called hardware mode. In order to activate watch-dog in this mode, the sequence 1E/E1(hex) should be written to the WDTRST register. After being set in this way, WDT cannot be disabled except by reset. In order to pre vent the hardware WCDT from resetting the entire device, the same sequence 1E/E1hex must be written to the same WDTRS before the timer nominal time is ran out.

WSWRST

When set, this bit resets watch-dog timer in software mode (bit HWDT=0). In order to enable the microcontroller to work normally, this bit must be regularly cleared from within the program. After being set by software, this bit is cleared by hardware during the next machine cycle.

If watch-dog is in hardware mode, this bit has no effect, and if set by software, it will not be cleared by hardware.

WDTEN

This bit enables/disables watch-dog timer in software mode (bit HWDT=0):

• 0 - Watch-dog halts
• 1 - Watch-dog starts counting

When watch-dog is in hardware mode (bit HWDT=1), this bit is read-only and reflects the status of the Watch-dog timer (whether it is turned on or off).

4.6 Interrupts

The AT89S8253 has a total of six interrupt sources, meaning that it can recognize up to 6 different events that can interrupt regular program execution. Each of these interrupts can be individually enabled or disabled by setting bits of the IE register while the whole interrupt system can be disabled by clearing the EA bit in the same register.

This microcontroller has embedded Timer T2 and SPI (they are not part of the “8051 Standard”). Since both of them can interrupt program execution, it was necessary to make minimal changes in registers that control interrupt system. A new interrupt vector (address 2B) is added, i.e. address in program memory from where the program continues its execution in case the Timer T2 causes interrupt. All these changes are only “added” to the positions of previously unused bits. This means that all programs already written for some of the former models of the microcontrollers can , with no changes, be executed in this one too. It is one of the main reason for popularity of all microcontrollers based on “noble gene” of the 8051.

IE register (Interrupt Enable)

EA Bit enables or disables all interrupt sources (globally):

• 0 - disables all interrupts (even it is enabled)
• 1 - allows those interrupts which are individually enabled

ET2 Bit enables or disables Timer T2 interrupt:

• 0 - Timer T2 can not cause interrupt
• 1 - Enables Timera T2 interrupt

ES Bit enables or disables serial communication (UART and SPI) interrupts:

• 0 - UART and SPI systems can not cause interrupts
• 1 - Enables UART and SPI interrupts

ET1 Bit enables or disables Timer T1 interrupt:

• 0 - Timer T1 can not cause interrupt
• 1 - Enables Timer T1 interrupt

EX1 Bit enables or disables external interrupt through the pin INT0:

• 0 - Changing of logical state on the pin INT0 can not cause interrupt
• 1 - Enables external interrupt at the moment of changing state on the pin INT0

ET0 Bit enables or disables Timer T0 interrupt:

• 0 - Timer T0 can not cause interrupt
• 1 - Enables Timer T0 interrupt

EX0 Bit enables or disables external interrupt through the pin INT1:

• 0 - Changing of logical state on the pin INT1 can not cause interrupt
• 1 - Enables external interrupt at the moment of changing state on the pin INT1

Interrupt Priorities

If multiple interrupts are enabled, it is possible to have interrupt requests during execution of another interrupt routine. In such situations, the microcontroller needs to resolve whether to proceed with the current interrupt routine or to meet a new interrupt request, which is based on priority levels. The former models of the microcontrollers differentiate between two priority levels defined in the IP register.

The AT89S8253 has additional SFR register IPH which assigns 1 of 4 priorities to each interrupt (excluding reset). The new list of priorities is as follows:

1. Reset. If there is a request for reset, all processes are stopped and the microcontroller behaves as if the power has just been turned on.
2. The highest priority interrupt (3). It can be stopped only by reset.
3. Lower priority interrupt (2, 1 or 0). It can be stopped by any interrupt with higher priority level.

It is usually defined at the beginning of the program which one of these existing inter rupt sources have higher and which one has lower priority level. According to this, the following occurs:

• If two interrupt requests, at different priority levels, arrive at the same time then the higher priority interrupt is always serviced first.
• If the both interrupt requests, at the same priority level, occur one after another , that one who came later has to wait until routine being in progress ends.
• If two interrupts of equal priority requests arrive at the same time then the interrupt to be serviced is selected according to the following priority list :

1. external interrupt INT0
2. Timer T0 interrupt
3. external interrupt INT1
4. Timer T1 interrupt
5. Serial communication Interrupt
6. Timer T2 Interrupt

IP register (Interrupt Priority)

This register bits determine the priority of interrupt sources.

PT2 Timer T2 interrupt priority

• 0 - Priority 0
• 1 - Priority 1

PS Serial port interrupt priority

• 0 - Priority 0
• 1 - Priority 1

PT1 Timer T1interrupt priority

• 0 - Priority 0
• 1 - Priority 1

PX1 External interrupt INT1 priority

• 0 - Priority 0
• 1 - Priority 1

PT0 Timer T0 interrupt priority

• 0 - Priority 0
• 1 - Priority 1

PX0 External interrupt INT0 priority

• 0 - Priority 0
• 1 - Priority 1

IPH register (Interrupt Priority High)

PT2H Timer T2 interrupt priority

PSH Serial port interrupt priority

PT1H Timer T1interrupt priority

PX1H External interrupt INT1 priority

PT0H Timer T0 interrupt priority

PX0H External interrupt INT0 Priority

Bits of this register can be combined with the appropriate bits of the IP register. The new priority list with 4 levels (5 including reset ) is based on it.

IP bit	IPH bit	Interrupts
0	0	Priority 0 (lowest)
0	1	Priority 1 (low)
1	0	Priority 2 (high)
1	1	Priority 3 (highest)

Handling interrupt

Upon receiving an interrupt requests, the microcontroller recognizes the source and following scenario takes place:

1. Ongoing instruction executed first.
2. Address of the instruction that would be executed next if there was no interrupt request is pushed on the stack.
3. Depending on the interrupt in question, the program proceeds with execution at one of five possible addresses according to the table below:

Interrupt Source	Jump Address
IE0	3h
TF0	Bh
IE1	13h
TF1	1Bh
RI, TI, SPIF	23h
TF2, EXF2	2Bh
All addresses are in hex format

These addresses should hold the appropriate subroutines for handling interrupt. Instead , there are usually instructions pointing to the locations where the appropriate subroutines reside (jump instructions).

4. When interrupt routine is executed, address of the next instruction to be executed is poped from the stack to the program counter and the program proceeds from where it left off.

4.7 Counters and Timers

Timers T0 and T1

The AT89S8253 has three timers/counters marked as T0, T1 and T2. Both timers T0 and T1 completely fall under the 8051 Standard. There are no changes in their operating.

Timer T2

Timer2 is the third 16-bit timer/counter installed only in newer models of 8051 family. Unlike timers T0 and T1, this timer comprises total of 4 registers. The first two, TH2 and TL2, are connected serially in order to form a bigger one, 16-bit counting register. Other two registers, RCAP2H and RCAP2L, are also connected serially and have the function to capture the contents of the counting register, i.e. the register in which counting is being executed is temporarily copied to them and vice versa .

The main adventage of this organization lies in the fact that all reading and swapping take place concurrently, using one instruction and with no need for programming acrobatics. Besides, T2 like older T0 and T1, has several different operating modes, which will be described later in this chapter.

T2CON (Timer/Counter 2 Control Register)

This register contains bits controlling the operation of T2.

TF2 - This bit is automatically set on counter overflow. In order to register next overflow, this bit needs to be cleared from within a program. If bits RCLK and TCLK are set, overflow has no effect on TF2.

EXF2 - This bit is automatically set whenever pulse on pin T2EX causes transfer from counting register to capture register or vice versa. If enabled, it gen erates interrupt, unless bit DCEN in T2CON register is set. EXF2 has to be cleared from within a program.

RCLK - This bit defines which timer determines receive rate of serial connection:

• 1 - Receive rate of serial connection is determined by T2
• 0 - Receive rate of serial connection is determined by T1

TCLK - This bit defines which timer determines transmit rate of serial connection:

• 1 - Transmit rate of serial connection is determined by T2
• 0 - Transmit rate of serial connection is determined by T1

EXEN2 - This bit involves pin T2EX in the operation of timer:

• 1 - Signal on pin T2EX has affect on the operation of timer
• 0 - Ignore logic state on pin T2EX

TR2 - This bit starts/stops timer T2

• 1 - Start Timer T2
• 0 - Stop Timer T2

C/T2 - Bit defines which pulses will be counted by counter/timer T2:

• 1 - 16-bit register (T2H and T2L) counts pulses on pin C/T2 (counter)
• 0 - 16-bit register (T2H and T2L) counts pulses from oscillator (timer)

CP/RL2 - Bit defines transfer direction:

• 1 - If enabled, (bit EXEN=1) pulse on pin T2EX will cause transfer from counter to capture register.
• 0 - Under same condition, signal on pin T2EX will cause transfer in the opposite direction – from capture to counter register.

Timer T2 in Capture mode

If bit CP/RL2 of register T2CON is set, timer T2 will operate according to the scheme presented below. This is the so called Capture mode in which value of the counter (comprises registers RCAP2H and RCAP2L) can be “captured” and copied to the capture register. The transfer has no effect on the counting process. How does the timer like this operate?

1. 16-bit register (TH2+TL2) holds the number from which the counting starts.
2. If set, bit TR2 of register TCON starts the timer. Each incoming pulse increments the value by 1. When both registers are full (decimal value of 65536), the first next pulse causes overflow, then reset occurs, and counting starts from zero.

Settings:

Timer T2 in Auto-reload mode

In order to set the timer T2 to Auto-reload mode, the bit CP/RL2 needs to be cleared. Then, the Timer will be able to count up or down from the specified value, depending on the bit DCEN in register T2MOD:

T2OE - Enables Timer to act as independent clock generator.

DCEN - When set, it enables counting in either direction- "up" and "down".

As it is presented in the scheme above, unlike Capture mode, the value of the capture register (RCAP2H, RCAP2L) is in this case copied to the counter (TH2, TL2) upon overflow.

Settings of Auto Reload mode are shown in the following table:

Everything previously stated on Timer T2 remains in effect only if register T2MOD hasn't been changed, i.e. if bit DCEN = 0. Otherwise, if this bit is set, timer (or counter) is enabled to count in either direction. Direction depends on logical state on the pin T2EX:

T2EX = 0 T2 counts down
T2EX = 1 T2 counts up

If counting up, situation is similar to the previously described mode with one exception concerning the bit EXF2 role.

If counting down, overflow occurs when values in the counting and capture registers match. At that moment, bit TF2 and all bits of registers T2H and T2L are set while the counting goes on “from the top” : 65535, 65534,65533...

In eather case, bit EXF2 is assigned a new role. Namely, upon overflow, this bit only inverts the signal and can not be used for generating interrupt anymore. Instead, this bit serves as supplementary bit (17th bit) of the counting register, making the counter virtually 17-bit register.

Timer T2 as clock generator in serial communication

If bits RCLK or TCLK of the register TCON are set, timer T2 turnes into clock generator (so called Baud Rate generator) which determines the transfer rate of serial communication. This mode is very similar to Auto-Reload mode with the rate of serial connection calculated according to the following formula:

Naturally, there are several specific details that should be taken into account:

1. Previous equation works only if the internal oscillator is used for counting ( in this mode, clock is divided by 2, instead of 12)
2. Overflow has no effect on bit TF2 and does not generate interrupt.
3. Whether the bit EXEN2 is set or not, logic state on T2EX has no effect on the counter. It means that pin T2EX can be used as an external interrupt source in this mode.
4. When working in this mode, timer should be turned off (TR2 = 0) ahead of writing or reading the contents of registers TH2 and TL2. Otherwise, an error in serial communication may occur.

Timer T2 as independent clock generator

In previous examples, pin P1.0 (marked as T2 in figures), serves as an alternative clock generator for this timer -i.e. it acts as input. It can be also used as output for generating sequence of pulses. Using the 16MHz quartz crystal, frequency of generated pulses ranges from 61Hz to 4MHz with pulse-to-pause ratio of 50%.

To configure the pin as output, bit C/T2 (in register T2CON) needs to be cleared, and bit T2OE (in register T2MOD) needs to be set. After that, bit TR2 starts the timer and the pin generates rectangular waves with frequency calculated according to the formula:

4.8 UART (Universal Asynchronous Receiver Transmitter)

Universal Asynchronous Receiver Transmitter UART preserved all the features of standard 8051 microcontrollers. It means that it can operate in 1 of 4 different modes, which is determined by bits SM0 and SM1 in register SCON.

Multiprocessor Communication

If using multiprocessor communication (bit SM2 in the SCON register is set), it is possible to automatically recognize microcontroller’s addresses. It enables easier program writing because the mutually connected microcontrollers don’t need to examine every serial address. How does it work?

Two new special Function Registers, SADDR and SADEN, enable it. Microcontroller’s address (an arbitrary number) is written to SADDR register, while so called address mask is written to register SADEN. The address mask is a binary number used to define which bits in the SADDR are to be used and which bits are to be ignored.

Since the bit SM2 is set, the microcontroller will recognize serial received 9-bit data as an address. Internal electronics immediately performs operation “logical AND” on these two registers and compares the result with received address. In that way, the processor recognizes whether upcoming data refer to it or not. Since some of the bits in address can be ignored (all corresponding bits with 0 in SADEN register), the data received via serial communication can be transferred to one, some or all microcontrollers which are mutually connected.

The most simple example is a “mini-network” comprising only 3 microcontrollers:

Microcontroller A is the master and communicate with devices “B” and “C”.

Microcontroller B: SADDR = 1100 0000
                   SADEN = 1111 1101
                 Address = 1100 00X0
                        
Microcontroller C: SADDR = 1100 0000
                   SADEN = 1111 1110
                 Address = 1100 000X

Although both microcontrollers B and C are assigned the same address (1100 0000), the mask in register SADEN is used to differentiate between these two slaves. It enables to communicate with both registers independently or at the same time:

If transmit address is 1100 0010, the data will be exchanged with slave device B.
If transmit address is 1100 0001 the data will be exchanged with slave device C.
If transmit address is 1100 0000 the data will be exchanged with both slave devices.

4.9 SPI System (Serial Peripheral Interface)

In addition to UART system, the AT89S8253 has also another system for serial communication which doesn’t fall into the 8051 Standard. It is SPI system which provides a high-speed synchronous data transfer between the microcontroller and one or more peripheral devices or between multiple microcontrollers. In such connection, one microcontroller is always considered as the main one- master device. It defines rate, transfer direction (whether the data are transferred or received) and data format. The other is slave device which is in subordinated position, meaning that it cannot start data transfer and has to adjust to conditions imposed by the master device.

The data are transferred via full duplex connection using 3 conductors connected to pins MISO (P1.6), MOSI (P1.5) and SCK (P1.7). The forth pin-control pin SS- is not in use on the master device and may be used as general-purpose input/output while on the slave device it must have voltage level 0. When pin SS on the slave device is set, its SPI system is deactivated and the MOSI pin can be used as a general-purpose input.

As it is shown in the scheme, pins MISO and MOSI perform differently on the master and slave device (as inputs or outputs), which is determined by the MSTR bit in register SPCR.

Like many other circuits inside the microcontroller, SPI system can also operate in several modes.

Normal SPI mode (buffer out of use)

After writting data to the SPI data register SPDR, it is automatically transferred to 8- bit shift register. SPI clock generator gets start and data in serial form appears on the pin MOSI. An initial delay may occur for synchronization with the main oscillator.

After shifting one byte, the SPI clock generator stops, bit SPIF(flag) is set, received byte is transferred to register SPDR and if enabled, an interrupt is generated.

Any attempt to write byte to register SPDR while a transmission is in progress, will set the WCOL bit, which indicates that error has occured. However, the transmission will be completed normally, meaning that error concerns new byte which will be ignored (byte will not be transferred).

Enhanced SPI mode (buffer in use)

Enhanced mode is similar to normal mode except that during transmission data goes through one more register. It doesn’t have any sense at first though, but connection is really enhanced in that way! Look at the figure below...

After writting data to the SPI data register SPDR, it is transferred to capture register (buffer), which automatically set bit WCOL signifying that the buffer is full and any further writes will cause overflow. Control electronics (hardware) cleares this bit upon the data from buffer is transferred to the shift register and its transmission in serial format begins. If this is the first byte in series, the data is immediately transferred to the shift register (still empty) and bit WCOL is immediately cleared (buffer is empty).

While this byte transmitting, the next byte may be written to register SPDR (it will be immediately copied to buffer). In order to know that sending data is in progress, it is sufficient to check if the bit LDEN (Load Enable) is set in register SPSR. When this bit is set and bit WCOL is cleared means that data transfer is in progress and that buffer is free so the next byte can be written to register SPDR.

How to select the right mode? If some individual byte is sent occasionally then there is no need to complicate- it is sufficient to set up the normal mode. If it is needed to send a great amount of data, it is better to use enhanced mode which offers obvious adventages: clock generator is not turned off as far as buffer is regularly kept full and as far as processor “see” set bit WCOL. In this mode, there is no wasting time for the sake of synchronization and data is easily transferred in format of long composition of bytes- as quick as lighting and with no holdups.

SPI system is under control of 3 SFRs: SPDR, SPSR and SPCR.

SPDR (SPI Data Register)

This is the register for storing data to be transferred via SPI (in serial format). It is also used for storing received data.

SPSR (SPI Status Register)

SPIF Interrupt flag. Upon data transfer, this bit is automatically set and an interrupt is generated if bits SPIE=1 and ES=1. The SPIF bit is cleared by reading SPSR followed by reading/writing SPDR register.

WCOL In normal mode (ENH=0), the bit is set if SPDR register is written during data transfer. It means that writing is premature and has no effect (It is called Write Collision). This bit is cleared in the same manner as the bit SPIF.
In enhanced mode (ENH=1), bit is set when buffer is full. It signifies that a new data “is waiting” for transmission to the shift register.

In enhanced mode, a new data can be written to buffer when this bit is set (if at the same time the bit WCOL=0).

DISSO When set, this bit causes the pin MISO to be floating, which make it possible that more than one slave microcontrollers can share the same interface with a single master. Normally, only the first byte in sequence could be the slave address, and all microcontrollers receive it. Afterwards, only one selected microcontroller should clear its DISSO bit.

ENH
0 SPI system is in normal mode (with no buffer)
1 SPI system is in enhanced mode

SPCR (SPI Control Register)

SPIE When this bit is set, SPI system can generate interrupt

SPE This bit “turns on” SPI system. When this bit is set, pins SS, MOSI, MISO and SCK are connected to microcontroller’s pins P1.4, P1.5, P1.6 and P1.7.

DORD Bit determines which bytes in serial connection goes first:

• 0 - When sending data MSB bit goes first
• 1 - When sending data LSB bit goes first

MSTR Bit determines whether microcontroller will operate as master or slave:

• 0 - SPI system operates as slave
• 1 - SPI system operates as master

CPOL Bit controls state on the pin SCK when the SPI system is on wait :

• 0 - During waiting, pin SCK is cleared
• 1 - During waiting, pin SCK is set

CPHA This bit along with the CPOL bit controls relation between clock and data in serial format (see table below).

SPR1,SPR0 When SPI system operates as master, these two bits determine boud rate, i.e. the frequency of clock signal of master device. When operates as slave , bits have no effect and SPI system is adjusted to the rate imposed by the master device.

SPR1	SPR0	SCK
0	0	Fosc/4
0	1	Fosc/16
1	0	Fosc/64
1	1	Fosc/128

Data format in case CPHA=0

* not defined. It is usually Msb byte previously received.

Data format in case CPHA=1

* not defined. It is usually Lsb byte previously received.

4.10 Power Consumption Control

Similar to all models belonging to the 8051 series, this microcontroller can operate in 1 of 3 modes: normal (consumption ca. 25 mA), Idle (consumption ca. 6.5 mA) and Power Down (consumption ca. 40 uA). Mode is selected by bits in register PCON (Power Control) with minimal supplements relative to the basic model:

PCON register

The purpose of bits in register PCON:

SMOD1 When set, this bit makes boud rate is two times faster.

SMOD0 Bit determines the purpose of the seventh bit in SCON register:

• 0 Seventh bit in register SCON has SM0’s role (selects mode)
• 1 Same bit has FE’s role (detecting errors). It is rarely used.

POF Bit is automatically set when, after turning on, the voltage level reaches maximum (must be higher than 3V). It is used for finding out/detecting causes for reset (turning on or restart after switching from Power Down mode).

GF1 General purpose bit (available for use)

GF0 General purpose bit (available for use)

PD When set, this bit sets up the microcontroller in Power Down mode

IDL When set, this bit sets up the microcontroller in Idle mode

Common mistakes (When things go wrong...)

If something unexpected happens, during the operation of the microcontrollers, what most bothers is the fact that it’s never up to the microcontroller. Although it’s not always obvious, the microcontroller will always obediently and consistently follow program instructions. For that reason, in order to avoid misunderstanding, special attention should be payed to several “critical points” when writing program. The first of them is RAM memory.

Even it is designed to meet needs of the majority of users, even it has all that is needed, a memory space intended for RAM is still only one single totality. It means that there are no phisically separated registers R0-R7, general purpose registers, stack etc. Instead, they all are differently designated parts of the same “memory shelf” (look at the figure)

If this “detail”, with a bit of negligence, is overlooked, there is a danger that program (or device) suddenly starts performs totally unpredictable. In order to prevent from such situations, attention should be payed to the following:

If only registers R0-R7 are in use, it is not possible that something unpredictable happens and memory locations at addresses from 08h are available for use. If registers from some other bank are in use (other registers with the same designations), be careful when using locations whose addresses are less than 20h because the contents of “R” registers can be erased.

If bit-variables are not used in the program, RAM locations at addresses 20h-2Fh are available for use. If there are such variables in the program, this space should be carefully used in order to avoid their accidental changes.

By default (if nothing has been changed), the data pushed on stack use RAM locations starting from address 08h. If the banks of registers 1, 2 or 3 are in use, their contents will be almost for sure unintentionally erased. For that reason, at the beginning ot the program, it is good to set value of Stack Pointer to be greater than 20h (more better-greater than 2Fh).

SFRs are in command to control and run microcontroller’s operation. Each of them has its specific purpose and so it should be. It means that they cannot be used as general purpose registers even in case that some of addesses in SFRs is not acctually in use.

In instruction set recognized by the microcontroller, there are such instructions which can be used for manipulating individual bits in the scope of register. Beside registers at addresses 20h - 7Fh, such direct access to individual bits is possible in some SFRs (not in all of them). Such SFRs are recognizable by their addresses divisible by 8.

If memory expanding is used (external RAM or ROM), complete ports P0 and P2 become unavailable regardless of how many pins are actually in use for communication with additional memory.

Register DPTR is a 16-bit register comprised of registers DPH and DPL which are 8-bit each. In practice, they should be treated like that. For example, if DPTR register should be pushed to the Stack, DPL should be pushed first, then DPH.

When serial communication is used, it is register SCON which controls this process. Since the Timer 1 is mostly used for boud rate generating than registers TCON and TMOD should be configured too.

When some of interrupts is enabled, one should be careful because there is danger that program starts executing in a strange way. What is all this about? When interrupt request arrives, the microcontroller will execute ongoing instruction, push address of the first following location on the stack (in order to know from where to continue) and jump to the address defined for interrupt requested. When subroutine has been executed, processor will pop address from the stack and will continue executing from where it left off. But...

The microcontroller “remembers” only return address. During subroutine execution, contents of many registers can be changed. When program continues execution after returning from subroutine, changed contents of registers will be treated as correct ones, if their previous values haven’t been saved, which can cause total chaos. The worst thing is that problem like this can be manifested anytime: at the moment or several days of work later (depending on the moment interrupt occurs). Obviously, the only solution is to memorize the state of all important registers in the beginning of interrupt routine and to turn these true values back to the program before returning from subroutine. The following registers are concerned:

• PSW
• DPTR (DPH, DPL)
• ACC
• B
• Registers R0 - R7

When some of instructions for indirect addressing are in use, one should pay attention to not use them for accessing SFRs because processor ignores their addresses and accesses free RAM locations which have the same addresses as SFRs.

When UART system for serial connection is in use, bits RI and TI of register SCON generate the same interrupt routine so one should first find out the cause of interrupt (byte is transferred, received or both). One should pay attention that processor only sets these bits! If one forget to clear these bits at the end of routine, the program gets stuck and repeats the same interrupt all the time.

Bit-addressable Registers List

Accumulator (Address: E0)

ACC
	After reset	0	0	0	0	0	0	0	0
	Bit name	-	-	-	-	-	-	-	-
	Bit address	E7	E6	E5	E4	E3	E2	E1	E0

B register (Address: F0)

B
	After reset	0	0	0	0	0	0	0	0
	Bit name	-	-	-	-	-	-	-	-
	Bit address	F7	F6	F5	F4	F3	F2	F1	F0

Interrupt Priority register (Address: B8)

IP
	After reset	X	X	0	0	0	0	0	0
	Bit name	-	-	PT2	PS	PT1	PX1	PT0	PX0
	Bit address	BF	BE	BD	BC	BB	BA	B9	B8

Interrupt Enable register (Address: A8)

IE
	After reset	0	X	0	0	0	0	0	0
	Bit name	EA	-	ET2	ES	ET1	EX1	ET0	EX0
	Bit address	AF	AE	AD	AC	AB	AA	A9	A8

Port 0 (Address: 80)

P0
	After reset	1	1	1	1	1	1	1	1
	Bit name	-	-	-	-	-	-	-	-
	Bit address	87	86	85	84	83	82	81	80

Port 1 (Address: 90)

P1
	After reset	1	1	1	1	1	1	1	1
	Bit name	-	-	-	-	-	-	-	-
	Bit address	97	96	95	94	93	92	91	90

Port 2 (Address: A0)

P2
	After reset	1	1	1	1	1	1	1	1
	Bit name	-	-	-	-	-	-	-	-
	Bit address	A7	A6	A5	A4	A3	A2	A1	A0

Port 3 (Address: B0)

P3
	After reset	1	1	1	1	1	1	1	1
	Bit name	-	-	-	-	-	-	-	-
	Bit address	B7	B6	B5	B4	B3	B2	B1	B0

Program Status Word (Address: D0)

PSW
	After reset	0	0	0	0	0	0	0	0
	Bit name	CY	AC	F0	RS1	RS0	OV	-	P
	Bit address	D7	D6	D5	D4	D3	D2	D1	D0

Serial Port Control register (Address: 98)

SCON
	After reset	0	0	0	0	0	0	0	0
	Bit name	SM0	SM1	SM2	REN	TB8	RB8	TI	RI
	Bit address	9F	9E	9D	9C	9B	9A	99	98

Timer Control register (Address: 88)

TCON
	After reset	0	0	0	0	0	0	0	0
	Bit name	TF1	TR1	TF0	TR0	IF1	IT1	IF0	IT0
	Bit address	8F	8E	8D	8C	8B	8A	89	88

Timer/Counter 2 Control register (Address: C8)

T2CON
	After reset	0	0	0	0	0	0	0	0
	Bit name	TF2	EXF2	RCLK	TCLK	EXEN2	TR2	C/T2	CP/RL2
	Bit address	CF	CE	CD	CC	CB	CA	C9	C8

Non Bit-addressable Registers List

Auxiliary register (Address: 8E)

AUXR
	After reset	X	X	X	X	X	X	X	0
	Bit name	-	-	-	-	-	-	Intel_Pwd_Exit	DISALE

Clock register (Address: 8F)

CLKREG
	After reset	X	X	X	X	X	X	X	0
	Bit name	-	-	-	-	-	-	-	X2

Data Pointer 0 High (Address: 83)

DP0H
	After reset	0	0	0	0	0	0	0	0
	Bit name	-	-	-	-	-	-	-	-

Data Pointer 0 Low (Address: 82)

DP0L
	After reset	0	0	0	0	0	0	0	0
	Bit name	-	-	-	-	-	-	-	-

Data Pointer 1 High Byte (Address: 85)

DP1H
	After reset	0	0	0	0	0	0	0	0
	Bit name	-	-	-	-	-	-	-	-

Data Pointer 1 Low Byte (Address: 84)

DP1L
	After reset	0	0	0	0	0	0	0	0
	Bit name	-	-	-	-	-	-	-	-

EEPROM Control (Address: 96)

EECON
	After reset	X	X	0	0	0	0	1	1
	Bit name	-	-	EELD	EEMWE	EEMEN	DPS	RDY/BSY	WRTINH

Interrupt Priority High Byte (Address: B7)

IPH
	After reset	X	X	0	0	0	0	1	1
	Bit name	-	-	PT2H	PSH	PT1H	PX1H	PT0H	PX0H

Power Control (Address: 87)

PCON
	After reset	0	X	X	X	0	0	0	0
	Bit name	SMOD	-	-	-	GF1	GF0	PD	IDL

Slave Address (Address: A9)

SADDR
	After reset	0	0	0	0	0	0	0	0
	Bit name	-	-	-	-	-	-	-	-

Slave Address Enable (Address: B9)

SADEN
	After reset	0	0	0	0	0	0	0	0
	Bit name	-	-	-	-	-	-	-	-

Serial buffer (Address: 99)

SBUF
	After reset	X	X	X	X	X	X	X	X
	Bit name	-	-	-	-	-	-	-	-

Stack Pointer (Address: 81)

SP
	After reset	0	0	0	0	0	1	1	1
	Bit name	-	-	-	-	-	-	-	-

SPI Control register (Address: D5)

SPCR
	After reset	0	0	0	0	0	1	0	0
	Bit name	SPIE	SPE	DORD	MSTR	CPOL	CPHA	SPR1	SPR0

SPI Data register (Address: 86)

SPDR
	After reset	-	-	-	-	-	-	-	-
	Bit name	-	-	-	-	-	-	-	-

SPI Status register (Address: AA)

SPSR
	After reset	0	0	0